With the continuous increase in the number of components that are designed into digital systems, there has also been a growing demand for practical means of verifying the design implemented. Historically, software simulation has been an invaluable aid in the verification process that is part of circuit design. However, for complex circuits, software simulation is notoriously slow and, even though the speed of computers has steadily increased, so has the complexity of the circuits being simulated. A solution to this problem is provided by hardware emulators. These are complex reconfigurable circuits that can emulate a variety of digital systems. They offer a very substantial speed increase over software only simulators.
A possible way of building such hardware emulators is to use programmable logic devices such as FPGAs (Field Programmable Gate Arrays). FPGAs are ideal as hardware emulators but, in order to make their use practical for large designs, a few problems need to be addressed.
In fact, if the design to be emulated is too large, it won't fit in a single FPGA. Consequently, the design will need to be split across multiple chips. Some FPGA vendors even provide design partition software with their tool suite (i.e., Altera Corporation). Once a complex circuit has been split over multiple FPGAs, a board can be easily built and the circuit emulated.
Unfortunately, this procedure presents a major drawback. In fact, during the verification process, design faults are very likely to be found, leading to modifications of the emulation board. Such modification will be very often necessary due to a variety of reasons, including the non-deterministic nature of the partition software for FPGAs. This would in turn be, in the great majority of the cases, too expensive and slow, especially in the beginning, when the number of faults discovered is likely to be fairly high. Clearly, what is needed is a board where the connections among the FPGAs are completely reconfigurable.
U.S. Pat. No. 5,447,475 by P. Sample et al., describes a digital emulator comprising an array of FPGAs provided with a richly interconnected architecture. Those skilled in the art will easily appreciate the high complexity and cost involved in building and programming effectively such a device. In fact, the large number of potentially high speed interconnections on the printed circuit board make it very expensive and difficult to manufacture and design. Also, the large number of variables and constraints involved in the partitioning and placement of large designs onto the array of FPGAs leads to very complex and slow software. This has the direct effect of slowing the turnaround time during the debugging process while requiring especially fast workstations.
Another approach is disclosed in U.S. Pat. No. 5,263,149 from T. Winlow (Winlow). Here a plurality of Programmable Logic Devices (PLDs) are connected via a shared data bus and programmable interconnect logic blocks (PILBs).
Unfortunately, this disclosure presents a series of fundamental problems in its practical implementation as well as being severely limited in the type of design that it can emulate. In fact, as it is stressed in the description and the claims of Winlow, only logic blocks with latched outputs can be simulated. As it can be readily acknowledged by those ordinarily skilled in the art, this is serious disadvantage. Not only components with purely combination outputs cannot be included in the emulation, but many latched blocks that don't fit in a single PLD must be excluded as well. This happens when a logic block cannot be split across multiple PLDs in a way that only presents latched outputs.
Further, the interconnection system described in Winlow presents practical problems. In fact, if we consider the circuit to be emulated divided in large blocks, then a relatively large number of I/O pins per block are likely to be necessary. This in turn implies a large bus and, more importantly, PILBs capable of selecting signals from a large set and transferring them to a multitude of input pins of the corresponding PLD. This last requirement is likely to make the PILBs complex and possibly slow. On the other hand, if the circuit is split into a large number of small blocks, each with a small number of outputs, then the practical problem of multiplexing many signals onto the shared data bus is self-evident.